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? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? 600 vdc drive for 270 vdc motors ? 10 amps @25c, 10 amps @85c ? 30 amps @25c, 30 amps @85c ? 75 amps @25c, 50 amps @85c ? half-bridge drive ? half-bridge drive with current sense ? half-bridge drive with regenerative clamp ? operates with brushless, brush, and induction motors ? input to output ground isolation with floating output stage ? short circuit protection ? trapezoidal or sinusoidal compatible ? dsp/microprocessor compatible description the pw-8x010p6, pw-8x030p6, and pw-8x075p6 series are half- bridge igbt drive modules containing isolated switch drivers, a pair of solid-state switches, and an isolated power supply. the magnum motor drive series are available in current ratings of 10, 30 and 75 amps. additionally, each current rating group is available with a cur- rent sense or a regenerative clamp feature to accommodate numer- ous design requirements. the three modules can be used in any com- bination to create drives for brush, brushless dc, or ac induction motors. the current sense signal and logic inputs are compatible with dsp/microprocessors and/or fpga/asic circuits used to control the motor drives. these modular drives are capable of operating from either a 135vdc or 270vdc power source that is electrically isolated from the logic input signals. the modules are fault tolerant from out- put shorts, loss of any or all power supplies, and power supply sequencing. applications the high reliability and flexibility of these drives make them suitable for military and aerospace applications. among the many applications are: actuator systems for primary and secondary flight controls on air- craft, fan and compressor motor drives for environment conditioning, pump motors for fuel and hydraulic fluid, antenna and radar position- ing, and thrust vector position control of missiles, drones, and rpv?s. all trademarks are the property of their respective owners. ? 1998, 1999 data device corporation pw-8x010p6, pw-8x030p6, pw-8x075p6 magnum motor drive? series 75a, 30a, 10a 600v magnum motor drives make sure the next card you purchase has...
2 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 figure 1a. pw-83010p6/83030p6/83075p6 block diagram figure 1b. pw-84010p6/84030p6/84075p6 block diagram figure 1c. pw-85010p6/85030p6/85075p6 block diagram power supply v cc v cc rtn sleep mode gate drive and fault control upper sc fault lower disable/reset power supply high drive low drive v bus + output v bus - auto reset i s o l a t i o n b a r r i e r power supply sleep_mode gate drive and fault control upper sc fault lower disable/reset power supply high drive low drive v bus + output v bus - current amp current amp r sense oc fault v iref v irsense_abs r sense + r sense - v cc v cc rtn v dd v dd_rtn v irsense auto reset i s o l a t i o n b a r r i e r power supply sleep_mode gate drive and fault control upper sc fault lower disable/reset power supply high drive low drive v bus + output v bus - ov amp regen status regen_clamp + auto reset ov_adj v cc v cc rtn regen_clamp - 5k ov_adj_low ov_adj_high i s o l a t i o n b a r r i e r
3 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 table 1. pw-8x010p6/8x030p6/8x075p6 absolute maximum ratings (tc = +25c unless otherwise specified) parameter symbol type units v irsense_abs output voltage r sense peak current (10ms, t c =85c) sc_f a ul t output voltage output current peak (10ms, t c =85c) continuous output current input logic voltage logic supply voltage drive supply voltage v irsense_abs i rsense.peak v oh i c.peak i c upper, lower, disable /reset , sleep_mode, a ut o reset v cc v bus + to v bus - pw-84xxx pw-84xxx all all all all all all vdc a vdc a a current amplifier supply voltage v dd pw-84xxx vdc vdc vdc vdc sc_f a ul t output current r sense continuous current v irsense output voltage i rsense i oh pw-84xxx all a ma v irsense pw-84xxx pw-8x010p6 value 5.5 36 5.5 110 75 5.5 5.5 600 5.5 30 8 5.5 pw-8x030p6 5.5 120 5.5 110 75 5.5 5.5 600 5.5 54 8 5.5 pw-8x075p6 5.5 220 5.5 110 75 5.5 5.5 600 5.5 100 8 5.5 vdc overvoltage transistor continuous current oc_f a ul t output current oc_f a ul t output voltage v irsense_abs output current i c i oh v oh i irsense_abs pw-85xxx pw-84xxx pw-84xxx pw-84xxx a ma vdc ma v irsense output current i irsense pw-84xxx ma reference input voltage overvoltage transistor collector-emitter voltage overvoltage transistor peak current (10ms, t c =85c) v ce v ref pw-85xxx pw-84xxx vdc vdc i c.peak pw-85xxx 40 20 5.5 20 20 600 5.5 85 40 20 5.5 20 20 600 5.5 85 40 20 5.5 20 20 600 5.5 85 a overvoltage flyback diode continuous current i d pw-85xxx 5 5 5 a overvoltage flyback diode peak current (10ms, t c =85c) i d.peak pw-85xxx 100 100 100 a regen_status output current v oh pw-85xxx 10 10 10 ma intermittent case operating temperature range t c.i all -55 to +125 -55 to +125 -55 to +125 c continuous case operating temperature range t c all -55 to +100 -55 to +100 -55 to +100 c storage temperature range t cs all -65 to +150 -65 to +150 -65 to +150 c junction temperature, power devices t j.power all +150 +150 +150 c junction temperature, other components t j.other all +135 +135 +135 c isolation voltage (note 1) v iso all 2500 2500 2500 vdc note 1: from v cc-rtn to v bus +, v bus -, output, regen_clamp+, r sense +, r sense -.
4 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 table 2. pw-8x010p6/8x030p6/8x075p6 general specifications common to all types (tc = -55c to 100c for min, max values, tc = 25c for typical values unless otherwise specified) parameter symbol test condition units output stage drive supply voltage transistors continuous output current capability peak current short circuit trip current saturation voltage turn-on energy per pulse turn-off energy per pulse flyback diode forward voltage reverse leakage reverse recovery peak current reverse recovery time v bus + to v bus - i c25 i c85 i c.peak i sc v ce(sat) e on e off v f i r irr (figure 2b) trr (figure 2b) unipolar/bipolar 25c case 85c case 85c case,<10ms note 1 ic = i c85 v ce = 270, ic = i c85, tj = 125c v ce = 270, ic = i c85, tj = 125c ic = i c85 85c case i f =i c85 and 85c case di/dt=480a/s i f =i c85 and 85c case di/dt=480a/s vdc a a a a vdc mj mj vdc ma a ns min typ max min typ max min typ max 10 10 110 200 270 350 1.5 0.3 0.6 1.4 15 130 600 2 1.8 6 30 30 110 200 270 350 1.8 0.9 1.6 1.6 17 150 600 2.2 2 6 75 50 110 200 270 350 2.2 1.5 2.7 1.7 19 175 600 2.6 2.1 6 output switching characteristics turn-on propagation delay turn-off propagation delay disable /reset delay to enabled disable /reset delay to disabled turn-on rise time turn-off fall time sleep_mode delay (from sleep) sleep_mode delay (to sleep) output switching frequency upper-lower deadtime requirement a ut o reset delay to output off a ut o reset delay to output on reset pulsewidth to clear sc f a ul t auto reset retry cycle time t d(on) (figure 2h) t d(off) (figure 2h) t d(on) (figure 2c) t dd (off) t r (figure 2h) t f (figure 2h) t dsleep(on) (figure 2d) t dsleep(off) (figure 2d) f pwm (figure 2a) t dead (figure 2a) t doff.auto t don.auto (figure 2f) t pw.reset (figure 2g) t cycle.auto (figure 2e) open collector source note 2 open collector source a ut o reset tied to sc f a ul t ns ns s ns ns ns ms ms khz s ms ms ns ms 150 640 100 140 0 2 200 40 27 850 2 3.7 202 3 100 650 1700 1700 200 200 150 640 100 140 0 2 200 40 27 850 2 3.7 202 3 100 650 1700 1700 200 200 150 640 100 140 0 2 200 40 27 850 2 3.7 202 3 100 650 1700 1700 200 200 control inputs a ut o reset , disable /reset , upper, lower high level input voltage low level input voltage hysteresis voltage upper, lower high level input current low level input current v ih v il v hyst i ih i il vcc=4.5v v ih =v cc v il =0v vdc vdc vdc a na 2.45 1.00 0.44 -1000 0.1 3.50 2.28 2.50 25 1000 2.45 1.00 0.44 -1000 0.1 3.50 2.28 2.50 25 1000 2.45 1.00 0.44 -1000 0.1 3.50 2.28 2.50 25 1000 pw-8x010p6 pw-8x030p6 pw-8x075p6 note 1: v bus + to v bus - must be > 10v (during short circuit for short circuit protection to operate). note 2: maximum output switching frequency limited only by junction temperature. note 3: tc refers to case temperature. note 4: n/a means 'not applicable'.
5 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 upper / lower output iout sc fault auto / reset t doff.auto t cycle.auto sleep_mode t d sleep (off) output high-z active active t d sleep (on) auto reset output t don.auto active high-z disable / reset t pw.reset scfault disable/reset output active active t d (off) high-z t d (on) 50a 0a -50a i f d i dt trr rr i ir table 2 timing diagrams figure 2d. sleep mode delay figure 2g. disable / reset pulse width figure 2h. output timing figure 2f. tdon.auto timing figure 2c. disable / reset propagation delay figure 2b. diode reverse recovery figure 2e. auto reset operation with short at turn on that clears figure 2a. standard timing operation upper/lower 50% t f t r output current 90% 10% 50% t d (on) t d (off) lower upper tdead 1 f pwm output v bus + v bus - high-z
6 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 control inputs (cont) disable /reset high level input current low level input current a ut o reset high level input current low level input current sleep_mode high level input voltage low level input voltage high level input current low level input current i ih i il i ih i il v ih v il i ih i il v ih =v cc v il =0v v ih =v cc v il =0v v ih =v cc v il =0v na a na ma vdc vdc na a -1000 -25 -1000 -1.6 2.4 -1000 -600 0.1 0.1 0.1 1000 1000 0.8 1000 -1000 -25 -1000 -1.6 2.4 -1000 -600 0.1 0.1 0.1 1000 1000 0.8 1000 -1000 -25 -1000 -1.6 2.4 -1000 -600 0.1 0.1 0.1 1000 1000 0.8 1000 control outputs sc f a ul t high level output current low level output current i oh i ol v oh =v cc v il =0.4v a ma 5 12 80 5 12 80 5 12 80 table 2. (cont) pw-8x010p6/8x030p6/8x075p6 general specifications common to all types (tc = -55c to 100c for min, max values, tc = 25c for typical values unless otherwise specified) parameter symbol test condition units min typ max min typ max min typ max pw-8x010p6 pw-8x030p6 pw-8x075p6 thermal thermal resistance - igbt - diode junction temperature range case operating temperature range storage temperature jc jc tj tc tc ts each output transistor each flyback diode output transistors & diode other components continuous <1% of the time c/w c/w c c c c c -55 -55 -55 -55 -65 0.45 0.8 0.55 0.87 +150 +125 +100 +125 +125 -55 -55 -55 -55 -65 0.45 0.8 0.55 0.87 +150 +125 +100 +125 +125 -55 -55 -55 -55 -65 0.45 0.8 0.55 0.87 +150 +125 +100 +125 +125 mechanical lead soldering temperature mounting torque power terminal torque d-connector screw torque weight note 1: v bus + to v bus - must be > 10v (during short circuit for short circuit protection to operate). note 2: maximum output switching frequency limited only by junction temperature. note 3: tc refers to case temperature. note 4: n/a means 'not applicable'. 10 seconds c in-lbs in-lbs in-lbs oz (g) 3 n/a n/a 250 6.5 3.1 (88) 3 n/a n/a 250 6.5 3.1 (88) 3 n/a n/a 250 6.5 3.1 (88)
7 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 table 3. specifications for current sense feedback pw-84xxx types (tc = +25c, v cc = v dd = 5.0v unless otherwise specified) parameter symbol test condition units v irsense gain * v irsense gain error v irsense gain drift v irsense offset * v irsense offset drift * v irsense output resistance v irsense output current v irsense_abs output resistance v irsense_abs output current v irsense_abs gain * error _absval * v irsense_abs gain drift v irsense_abs offset * v irsense_abs offset drift sense resistor, resistance delay time bandwidth linear range oc_f a ul t trip level trip delay time reference voltage input current reference voltage input reference voltage input capacitance g vout e vout tc gvout v os tc vos r out i vout r abs i abs g vabs e vabs absgdrift v osabs tcv osabs r sense t delay (figure 3a) f bw (figure 3b) i range i oc t ioc (figure 3c) i vref v ref c vref v ref = 5.0v v ref = 5.0v v ref = 5.0v v ref = 5.0v v ref = 5.0v -55 to +100c -55 to +100c -55 to +100c -55 to +100c -55 to +100c (10k pull up to v dd ) -55 to +100c -55 to +100c mv/a % ppm/c mv v/c ma ma mv/a mv ppm/c mv v/c m-ohm s khz a a s ma vdc f min typ max min typ max min typ max -5 -330 -31 -115 1 1 -116 -131 -90 20 10.4 4 218.3 20 0.2 3 0.3 3 436.5 30 330 22 9 30 9.1 11.6 3 0.26 0.1 5 330 31 115 116 131 110 20 12.7 6 1 v dd -5 -330 -31 -115 1 1 -116 -131 -90 20 33.8 4 67.46 20 0.2 3 0.3 3 134.9 30 330 6.8 9 30 30 37.6 3 0.26 0.1 5 330 31 115 116 131 110 20 41.2 6 1 v dd -5 -330 -31 -115 1 1 -116 -131 -90 20 115 4 19.84 20 0.2 3 0.3 3 59.52 30 330 2 9 30 100 128 3 0.26 0.1 5 330 31 115 116 131 110 20 140 6 1 v dd oc_fault (-55 to +100c) high level output current low level output current i oh i ol v oh =v dd v ol =0.8v a ma 4 0.2 15 4 0.2 15 4 0.2 15 * note: these parameter values are proportional to v ref . values shown are at v ref = 5v; when different v ref values are used, these values should be scaled accordingly. for example when operating at v ref = 4v, multiply each of the asterisk values by 0.8. the v irsense_abs output is intended for use in gross overcurrent detection. for accurate current measurements v irsense should be used. the equation below shows how the specifications are used to compute overall error in v irsense .( t is the change in ambient temperature from 25c). pw-84010p6 pw-84030p6 pw-84075p6 v irsense = { v irsense.gain ? ( ) ? (1 + v irsense.gain.error ) ? (1 + v irsense.gain.drift ? t) } ? i rsense + v irsense.offset ? ( ) + v irsense.offset.drift ? ( ) ? t + ( ) v ref 5v v ref 5v v ref 5v v ref 2 v irsense.abs = | { error _absval ? ( ) + 2 ? (v irsense - ) } | v ref 5v v ref 2 the equation below shows how to compare overall error in v irsense.abs .v irsense.abs is an output derived from v irsense . the v irsense error is composed of all v irsense errors with the addition of the error_absval. i resense oc_fault ioc t ioc 0a v dd 0v 0 5 10 15 20 25 30 35 40 45 50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v irsense v irsense_abs i rsense v irsense step response time (s) volts or %irange (normalized to irange) t delay 50% v irsense_abs 50% v irsense 50% i rsense (normalized) (v ref = 5.0 v) 1 10 100 1 10 100 virsense bandwidth frequency of i_rsense (khz) virsense gain bw f -3db figure 3c. oc fault trip response time figure 3a. v irsense step response figure 3b. v irsense bandwidth
8 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 table 4. specifications for overvoltage protection pw-85xxx types (v cc = 5.0v unless otherwise specified, t c = -55c to +100c for min, max values, t c = +25c for typical values unless otherwise specified) parameter symbol test condition units overvoltage protection circuit transistor collector-emitter voltage continuous current peak current saturation voltage reverse leakage flyback diode forward voltage reverse leakage v ce i c25 i c85 i c.peak v ce(sat) i r v f i r 25c case 85c case 85c case, <10ms @ i c85 85c case @ i c85 85c case vdc a a a vdc ma vdc ma min typ max min typ max min typ max 40 30 85 2.00 1.40 600 3.00 0.4 1.73 2 40 30 85 2.00 1.40 600 3.00 0.4 1.73 2 40 30 85 2.00 1.40 600 3.00 0.4 1.73 2 regen status overvoltage trip threshold overvoltage threshold hysteresis high level output voltage low level output voltage output resistance v bus + crossing upper threshold to status on delay v bus + crossing lower threshold to status off delay vbus+ crossing upper threshold to transistor on delay vbus+ crossing lower threshold to transistor off delay v upper v hyst v oh v ol r o t don.status t doff.status t don.transistor t doff.transistor referenced to v bus - or regen_clamp- without external adjustment no load, v bus + > upper threshold no load, v bus + < lower threshold @ i c85 @ i c85 vdc vdc vdc vdc k ns ns ns ns 358 34 14.00 0.00 4.5 400 40 15.00 0.05 4.75 36 48 36 49 440 45 15.75 0.20 5.2 358 34 14.00 0.00 4.5 400 40 15.00 0.05 4.75 36 48 36 49 440 45 15.75 0.20 5.2 358 34 14.00 0.00 4.5 400 40 15.00 0.05 4.75 36 48 36 49 440 45 15.75 0.20 5.2 thermal thermal resistance - igbt - diode jc jc c/w c/w 0.8 12 1.2 18 0.8 12 1.2 18 0.8 12 1.2 18 pw-85010p6 pw-85030p6 pw-85075p6
9 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 table 5. power supply specifications for all types (v cc = v dd = 5.0 v unless otherwise specified, t c = -55c to 100c for min, max values, t c = 25c for typical values.) parameter symbol test condition units supply voltage for pw-83xxx types supply current for pw-83xxx types v cc i cc i cc.sleep note 1 in sleep_mode vdc ma ma min typ max min typ max min typ max 4.5 5 110 11 5.5 200 4.5 5 110 11 5.5 200 4.5 5 110 11 5.5 200 supply voltage for pw-84xxx types supply current for pw-84xxx types current sense amplifier supply current v cc , v dd i cc i cc.sleep i dd note 1 in sleep_mode vdc ma ma ma 4.5 5 136 11 10 5.5 200 20 4.5 5 136 11 10 5.5 200 20 4.5 5 136 11 10 5.5 200 20 supply voltage for pw-85xxx types supply current for pw-85xxx types note 1: during initial power-on, a transient current of up to 100ma above i cc may be observed until v cc exceeds about 3.5 volts for the pw-8x010, pw-8x030 and pw-8x075. v cc i cc i cc.sleep note 1 in sleep_mode vdc ma ma 4.5 5 137 11 5.5 250 4.5 5 137 11 5.5 250 4.5 5 137 11 5.5 250 pw-8x010p6 pw-8x030p6 pw-8x075p6
10 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 introduction the pw-8x010p6, pw-8x030p6 and pw-8x075p6 magnum families are a series of universal modular half-bridge motor drives intended for use with brush, brushless dc and ac induc- tion motors in ground, sea and aerospace applications. the pw-8x010p6, pw-8x030p6 and pw-8x075p6 motor drives contain an isolation barrier between the power and con- trol stages, which attenuates ground noise generated from the high speed, high power switching. all signals from the control to the power sections are isolated from power and ground of the other section. this eliminates false triggering of the input signals and any need for creative grounding schemes. the isolation bar- rier also allows the user to operate the output stage from either unipolar or bipolar power supplies without level shifting the input signals. a built in power supply located in the control stage pro- vides power to all electronics in the power stage. this eliminates the need for refresh cycles or external power supplies for the gate drive circuitry and allows switching duty cycles from 0 - 100%. (reference figures 1a, 1b, 1c) the output power transistors on all modules are protected from a short circuit applied to the output pin. when a short circuit condition is detected, the output transistors are shut down and a flag sc f a ul t is made active (logic low (l)) indicating a short has occurred. the pw-84010p6, pw -84030p6 and pw-84075p6 modules con- tain additional current sensing circuitry that can monitor either motor current or dc bus current. the output voltage of the current sensing circuit can be used as a feedback signal in a servo drive to create a torque loop (reference figure 1b). all output power transistors can be protected from regenerative bus overvoltage when utilizing dynamic braking with the addition of one pw-85010p6, pw-85030p6 or pw-85075p6 module. this module contains an overvoltage switch that is enabled when an overvoltage condition is detected. this switch is normally wired to an external (user supplied, application specific) load dump resis- tor to provide a load across the high voltage bus when overvolt- age is detected. during an overvoltage condition, the status flag regen_status is active (logic high (h)) indicating an overvolt- age condition is occurring. (reference figure 1c) pw-8x075p6, pw-8x030p6 and pw-8x010p6 i/o and operation upper, lower (inputs) upper and lower are active high cmos schmitt-trigger inputs that control the gate drives of the output transistors (ttl compatibility requires external 10k pull-up resistors). each input is electrically isolated from the output. as shown in figure 4, a dead band (reference t dead in table 2) between turn off and turn on of upper and lower inputs is necessary to prevent output shoot through conduction. sc f a ul t (output) sc f a ul t is an active low open collector output signal that indi- cates when the output of the module has experienced a short cir- cuit condition. sc f a ul t will remain active until disable /reset is made active (l). the signal is inactive (high impedance) during normal operation. see short circuit protection for more detail. disable / reset (input) disable / reset is an active low cmos schmitt-trigger input. when disable / reset is held active it does two things: 1.) resets the sc f a ul t (if it was active), and 2.) disables the out- put (makes the output high impedance). if this line is used sole- ly to clear sc f a ul t then it only needs to be pulsed active. the duration of the disable / reset active pulse must be at least tpw.reset to ensure that sc f a ul t is cleared properly. when this line is inactive, the output is allowed to respond to the other control lines of the module (upper, lower, sleep_mode). note: ttl compatibility requires an external pull-up resistor. a ut o reset (input) a ut o reset is an active low (l) input. when a ut o reset is tied to sc f a ul t the protection circuit will reset automatically after the short circuit fault has occurred, and a delay period, tcycle.auto, has expired. this automatic reset enables the output to respond to the input commands. see short circuit pro- tection for more detail. sleep_mode (input) sleep_mode is an active high input that turns the internal power supply off. a logic low (l) enables the power supply and allows the motor drive to operate normally. a logic high (h) on the sleep_mode input disables the internal power supply, disabling the motor drive output. no damage will occur to the motor drive during turn on or turn off of the power supply. additionally, no special power up sequence is required. the upper and lower logic gate driver inputs should not be active while transitioning in and out of sleep mode. if the upper and lower logic inputs must be active while entering sleep t dead 50% upper lower 50% 50% 50% t dead figure 4. pw-8x010p6, pw-8x030p6 and pw-8x075p6 dead band requirement
11 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 mode then disable / reset must be held active while coming out of sleep mode. note: sleep_mode has an internal pull-up resistor. if the input is not connected, it will default to logic high, turning the power supply and the motor drive off. v cc ,v cc-rtn (inputs) the v cc and v cc-rtn are power connections that supply input power to the internal power supply, the gate drive and fault control circuits. v bus +, v bus - (inputs) v bus + and v bus - are the high voltage power connections to the output stage. the high voltage can be either unipolar (+v and ground) or bipolar (+/- v). care must be taken to ensure that the transient bus voltage v bus at the module terminals never exceeds the absolute maximum supply ratings during switching excursions. external capacitor filtering will be required (see ddc?s applications note an/h-7). output (output) output is the power switch output that is connected to one input of the motor and applies v bus +, v bus -, or high impedance to the motor based on the state of the control inputs. it is capable of sourcing or sinking up to the rated output current, and can with- stand a short circuit to v bus + or v bus - without any damage by automatically turning itself off (high impedance state). short circuit protection the pw-8x010p6, pw -8x030p6 and pw-8x075p6 modules have provisions for complete short circuit protection from either a hard or soft short to the v bus + or v bus - lines. each output tran- sistor on all pw-8x010p6, pw -8x030p6 and pw-8x075p6 mod- ules are protected from a hard (direct, low impedance) short to the v bus + or v bus - lines by circuitry that detects the de-saturation voltage for that transistor during a short condition. once a hard short circuit condition is detected, the affected output transistor is shut down and sc f a ul t output is set active (logic low (l)). the sc f a ul t signal can be used by a controller as a signal to initiate a fault routine to reset or shut down the system. the disable / reset input can be used to shut down the gate drivers if a short persists. if the a ut o reset is tied to sc f a ul t , the circuit will automatically reset when a fault occurs. this inactivates sc f a ul t and reactivates the output transistor within the tcycle.auto time period. if the short is still present, the circuit will repeat the shut down and automatically reset until the short is clear. protection against a soft-short requires the addition of current sensing magnum motor drive modules and external circuitry. when a soft short occurs, the external circuit can set disable / reset low (l) to shut down the gate drivers. pw-84010p6, pw-84030p6 and pw-84075p6 i/o and operation pw-84010p6, pw -84030p6 and pw-84075p6 modules can be added to a motor drive to provide current monitoring and overcur- rent protection capability. the following section describes the pw- 84010p6, pw -84030p6 and pw-84075p6 modules and their fea- tures. v dd , v dd-rtn v dd and v dd-rtn supplies input power to the current amplifier. v irsense (output) v irsense is an output that provides a voltage proportional to the current passing through r sense . the voltage is scaled by a ref- erence voltage v ref and is equal to v ref /2 to represent zero current. a voltage greater than v ref /2 indicates a positive cur- rent flow (positive voltage from r sense + to r sense -) through r sense . see figure 1b. this v irsense voltage is scaled by the input voltage at v iref , where: v irsense = (v ref /2) + (v irsense gain) * (i rsense ) or v irsense = (v ref /2) + (v ref / . 504* r sense ) * (i rsense ) note: i rsense is current flowing through r sense (refer to table 3 for r sense value). zero amps in r sense is indicated when v irsense = v ref /2. a voltage greater (less) than v ref /2 indi- cates a positive (negative) current flow through r sense with a value defined by the v irsense equation. v irsense is electrically isolated from the output stage. a positive (negative) current flow from r sense + to r sense - produces a positive (negative) volt- age measurement (see figure 1b). when the power supply is shut down (sleep_mode input high), the voltage at v irsense will indicate 0v. note: during normal operation 0 volts at v irsense represents maximum negative current. v ref (input) a precision voltage reference from an external source is con- nected to the v ref pin to set the output voltage scale for v irsense and v irsense_abs . note: the accuracy of the v irsense and v irsense_abs outputs are subject to the accuracy and tem- perature coefficient of v ref . these must be taken into account in calculating the overall accuracy of v irsense . r sense +, r sense - (inputs) the r sense + and r sense - pins are connected to an internal shunt resistor and monitoring circuitry. these pins can be con- nected anywhere within the isolation restrictions on the pins (600v to power pins, 2500v to logic pins). these pins are typi-
12 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 cally connected in series with the output, v bus + or v bus -, to measure motor drive current. v irsense_abs (output) v irsense_abs output voltage is the absolute value of the v irsense voltage signal. v irsense_abs is zero volts when there is no current flowing through the r sense resistor. it will increase towards the value of v iref as the current in r sense approaches either full-scale current (measurement limits of v irsense ). v irsense_abs is an open source output and is "wire-or-able". when two or more v irsense_abs outputs are "wire-or-ed", the highest voltage will appear on the common signal. a typical use for combining these outputs is for determining when an overload condition has occurred. the v irsense_abs voltage is scaled by the input voltage v irsense where: v irsense_abs = 2 x | v irsense - v ref /2 | oc f a ul t output oc f a ul t is an active low open drain output that goes active when the current flowing through r sense has exceeded the oc f a ul t trip level. this signal is not latched like sc f a ul t , and goes inactive as soon as the over current condition stops. pw-85010p5, pw-85030p6 and pw-85075p6 i/o and operation pw-85010p6, pw-85030p6 and pw-85075p6 modules can be added to a motor drive to provide overvoltage protection capa- 10 100 1000 350 375 400 425 450 475 500 525 550 trip voltage, (vdc) resistance, (kohms) ov switch on ov switch off v hyst vtrip 1 10 100 1000 10000 0 50 100 150 200 250 300 350 400 trip voltage, (vdc) resistance, (kohms) ov switch on ov switch off v hyst vtrip figure 5a. external ov adjust resistor connected to ov_adj_high figure 5b. external ov adjust resistor connected to ov_adj_low bility. the following section describes the pw-85010p6, pw- 85030p6 and pw-85075p6 modules and its features. regen_status (output) the regen_status pin is referenced to v bus -, and indicates the state of the regen clamp switch (h = on, l = off). an external opto- isolator input can be connected between regen_status and v bus - to translate this status to logic circuits if desired. the regen_status output is connected to the overvoltage amp through a 5k resistor. when the regen clamp switch is active (inactive), the overvoltage amp sources +15v (0v) through the 5k resistor. (see figure 1c). regen_clamp (output) (ref. r20 on figures 11 and 12) an external load dump resistor is connected between regen_clamp and v bus +. when v bus + reaches the overvolt- age trip level set by the ov_adj, the internal clamp circuit will apply the load dump resistor from v bus + to the v bus -, thereby dissipat- ing the regenerative energy of the bus into the external resistor. ov_adj (input) the pw-85010p6, pw-85030p6 and pw-85075p6 modules are internally set for a trip voltage of 400v. the trip point can be adjusted to a higher or lower voltage by connecting an external overvoltage adjust resistor r ov_adj (ref. r21 on figures 11 and 12). to set the overvoltage trip point to a voltage above 400 volts con- nect r ov_adj between the ov_adj and ov_adj_high pins. to set the ov trip point to a voltage below 400 volts connect pw-8x075p6, pw-8x030p6 and pw-8x010p6 typical overvoltage trip vs. ov adjust settings
13 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 10% 90% t d (off) 10% 90% 5% v bus o i d (on) t r f t t upper / lower on ps- t on off ps- figure 7. output characteristics figure 6. 2 quadrant power dissipation circuit r ov_adj between the ov_adj and ov_adj_low pins. the value of r ov_adj for voltages above (below) 400 volts should be selected based upon figure 5a (5b). power dissipation there are three major contributors to power dissipation in the motor drive: conduction losses, switching losses, and flyback diode losses. consider the following arbitrary operating condi- tions for the 2 quadrant example using the pw-8x075. v bus = v ce = +200v f pwm = 10khz duty cycle = 50% (ton = 50s; toff = 50s) i o = i c = 40a, module output current (see figure 6) during toff, if = i o the power dissipation of the 2 quadrant example circuit shown in figure 6 can now be calculated using information from the data sheet as follows: q1 - transistor data (output stage) t j max = 150 c (table 2) jc.igbt = 0.55c/w (table 2) v ce(sat) = 2.2v e on (50a, 270v) = 1.5 mj (table 2) e off (50a, 270v) = 2.7 mj (table 2) cr1 - flyback diode data t j max = 150 c jc. diode = 0.87c/w (table 2) v f (avg) = 1.7v 1. q1 transistor conduction losses (p c ) p c = ic x v ce(sat) x duty cycle p c = 40a x 2.2 x 50% p c = 40a x 2.2 x 0.5 p c = 44w 2. q1 transistor switching losses (p s ) ps = [e on (scaled) + e off (scaled)] x f pwm note: e on/off (scaled) from conditions in table 2. e on (scaled) = ( e on @ 50a, 270v) x (v bus / 270v) x (i o / 50a)] e on (scaled) = [(1.5mj) x (200v / 270v) x (40a / 50a)] e on (scaled) = 0.88 mj e off (scaled) = [(e off @ 50a, 270v) x (v bus /270v) x (i o /50a)] e off (scaled) = [(2.7 mj) x (200v/270v) x (40a/50a)] e off (scaled) = 1.6 mj p s = (0.88 mj + 1.6 mj) x 10khz p s = 24.8w 3. cr1 flyback diode losses (pd) pd = i c x v f (avg) x [1 - duty cycle] pd = 40a x 1.7v x [1 - 50%] pd = 40a x 1.7v x [1 - 0.5] pd = 40a x 1.7v x 0.5 pd = 34w 4. q1 transistor power dissipation (p t ) p t = p c + p s p t = 44w + 24.8w p t = 68.8w 5. maximum allowed module case temperature t case.allowed.igbt = tjmax - jc. igbt x p t t case.allowed.igbt = 150c - [(0.55c/w) x (68.8w)] t case.allowed.igbt = 112c t case.allowed. diode = t jmax - jc. diode x pd t case.allowed. diode = 150c - [(0.87c/w) x (34w)] t case.allowed. diode = 120c maximum allowed case temperature for the module will be the lesser of the allowed diode and allowed igbt case tempera- pw-8x010p6, pw-8x030p6 and pw-8x075p6 v bus+ v bus- output motor a b c io ton 1/f pwm ic if toff q1 cr1
14 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 position command position error velocity command velocity error torque command torque error current error amp pwm magnum 3-module set 3-phase motor torque loop velocity loop position loop + - + - + - motor angle / position information (hall / resolver / encoder) velocity error amp position error amp x = indicates that this input is irrelevant. z = high impedance (off). * = fault will disable the transistor that caused the fault. the output state could be z or on. disable/ reset lower z 1 0 x v bus - 0 v bus + x z 0 0 z 1 1 1 * 1 1 * z 1 table 6. pw-8x010p6, pw-8x030p6 and pw-8x075p6 truth table 0 x x 0 1 x x 1 1 0 x upper sleep- mode sc-fault out 0 0 x x 0 x 1 0 1 1 x x 0 x x 0 figure 8. typical position, velocity and torque control loop
15 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 applications position or velocity control using dsp figure 11 shows an example of position and/or velocity control hook-up with inner torque loop using the digital signal processor (dsp) for motor control. using software, the dsp can be implemented with one of several motor control algorithms such as foc (field oriented control) with svm (space vector modulation). torque control using uc2625 motor con- troller figure 12 shows an example of torque control loop with regen- erative clamp protection using a uc2625, two pw-84010p6, pw-84030p6 or pw-84075p6 modules, and one pw-85010p6, pw-85030p6 or pw-85075p6 module. the two pw-84010p6, pw-84030p6 or pw-84075p6 modules (? bridge with current sense) sense the current in motor phase b and c. v irsense pins on each of the pw-84010p6, pw-84030p6 or pw-84075p6 modules are connected to the decommuntation circuit (shown in figure 14) to produce bipolar output voltage that is compared to the torque commanded input to produce an error signal. the uc2625 uses this error signal to regulate the output current (or torque) by controlling the duty cycle of the output transistors. the gain of the current decommuntation circuit shown in figure 14 has been selected to accommodate a 10v command input volt- age. for the case when a resolver is available instead of hall-effect devices, the circuit shown in figure 13 converts the resolver (sin and cos) signals to hall signals which can be used to com- mutate the output transistors. hall signal commutation the hall signals hab, hbc, hca are logic signals from the motor hall-effect sensors. the uc2625 uses a phasing conven- tion referred to as 120 degree spacing; that is, the output of hab is in phase with motor back emf voltage vab, the output of hbc is in phase with motor back emf voltage vbc, and the output of hca is in phase with motor back emf voltage vca. logic "1" (or high ) is defined by an input greater than 2.4vdc or an open cir- cuit to the controller; logic "0"(or low) is defined as any hall voltage input less than 0.8vdc. the uc2625 will operate with hall phasing of 60 or 120 elec- trical spacing. if 60 commutation is used, then the output of hca must be inverted as shown in figures 9 and 10. in fig- ure 9 the hall sensor outputs are shown with the corresponding back emf voltage they are in phase with. hall-effect sensor phasing vs. motor back emf for cw rotation (120 commutations) 300 0 60 120 180 240 300 360 /0 60 v ab v bc v ca back emf of motor rotating cw cw hab hbc hca hca in phase with v ab in phase with v bc in phase with v ca in phase with v ac (60?) figure 9. hall phasing s hca hab 120 n hbc 120 n hca 120 remote position sensor (hall) spacing for 120 degree commutation 60 60 remote position sensor (hall) spacing for 60 degree commutation s hab hbc hca figure 10. hall sensor spacing
16 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 +5v c10 + c11 motor power supply +270v r20 c8 + c9 power rtn motor sleep_mode v cc upper lower sc fault disable/reset v cc-rtn regen_status v bus + output v bus - regen - clamp+ upper lower sc fault oc fault v ir sense v ref upper lower sc fault v ref v bus + output v bus - r sense + r sense - v bus + output v bus - r sense + r sense - pw-85010p6, pw-85030p6 or pw-85075p6 sleep_mode sleep_mode disable/reset disable/reset oc fault v cc v cc-rtn v cc v cc-rtn v dd v dd-rtn v dd v dd-rtn (4) auto reset auto reset auto reset regen- clamp- vref a / d ch. 1 ua la ub lb uc lc a / d ch. 2 interrupt dsp motor controller position or velocity command resolver r/d converter rd-19230 (see resolver-to-hall signal conversion circuit) vcc vdd vdd rtn i / o i / o i / o i / o i / o r22 c12 c13 r23 ov_adj ov_adj_high ov_adj_low r21 (4) v ir sense pw-84010p6, pw-84030p6 or pw-84075p6 pw-84010p6, pw-84030p6 or pw-84075p6 figure 11. pw-8x010p6, pw-8x030p6 and pw-8x075p6 position or velocity hook-up using dsp motor controller notes: 1. c8 is a ceramic capacitor and should be selected per ddc application note an/h-7, pw-82351 motor drive power supply, equation 1. 2. c9 is an electrolytic capacitor and should be selected per ddc application note an/h-7, pw-82351 motor drive power supply, eq uation 1. 3. c10 is 22 f, 15 v electrolytic capacitor. c11 is 0.1 f, 50 v ceramic capacitor. 4. resistance and power of r20 (load dump resistor), and r21 (ov adjust resistor) is application specific. (see ov adjust and rege n description for details)
17 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 +15v +5v c10 + c11 motor power supply +270v r20 c8 + c9 power rtn r19 10k (8) r18 5k 0.01f c7 r17 10k 10m cr4 3.3v 1n746 cd4050 cd4049 c6 0.1f r15 10k r14 10k r13 10k +5v 19 11 18 14 hca hab hall supply +5v motor lm741 r11 1m r6 1k +5v command signal input 3.3v 1n746 cr5 10k (8) 10k 10k (8) 100 lm741 r10 r12 r22 r9 10k (8) r23 cd4049 1/6 1/6 1/6 1/6 q1(9) sleep_mode v cc upper lower sc fault disable/reset v cc-rtn regen_status ov adj v bus + output v bus - regen_ clamp+ upper lower sc fault oc fault v irsense v iref upper lower sc fault v iref v bus + output v bus - r sense + r sense - v bus + output v bus - r sense + r sense - hall rtn 10k v- v- 10k v- 10k uc-2625 sleep_mode sleep_mode disable/reset disable/reset oc fault (10) (10) (10) (11) (11) (11) (11) (11) (11) (11) (11) v cc v cc-rtn v cc v cc-rtn v dd v dd_rtn v dd v dd_rtn (4) auto reset auto reset auto reset regen_ clamp- v irsense_abs v irsense_abs v irsense v irsense_c v irsense_b icomp hca hab hbc v iref v iref v ref current decommutation circuit (see figure 14) -15v +5v r21 (4) ov_adj_high ov_adj_low a b c +15v hbc hall sensor inputs r1 100 r2 100 c1 2000pf c2 2000pf c3 2000pf r3 100 hca hab hbc 9 8 10 h1 h2 h3 vcc pwr-vc pua pda pub pdb puc pdc isense a isense b gnd quad-se rc-osc pwm-in e/a out e/a in- dir e/a in+ isense s-start rc-brake tach-out ov-coast speed-in r4 10k r5 2k lm111 r7 20k c5 0.001f 7 23 20 21 24 3 1 6 28 27 2 22 25 26 c4 0.01f r16 15 5 4 12 16 17 13 r24 10k r25 10k r26 10k +5v pw-84010p6, pw-84030p6 or pw-84075p6 pw-84010p6, pw-84030p6 or pw-84075p6 pw-85010p6, pw-85030p6 or pw-85075p6 i a i b i c (+/- 10v for full scale) + = cw - = ccw (13) (13) (13) notes: 1. c8 is a ceramic capacitor and should be selected per ddc application note an/h-7, magnum motor drive power supply capacitor s election. 2. c9 is an electrolytic capacitor and should be selected per ddc application note an/h-7, magnum motor drive power supply capac itor selection. 3. c10 is 22 f, 15 v electrolytic capacitor. c11 is 0.1 f, 50 v ceramic capacitor. 4. resistance and power of r20 (load dump resistor), and r21 (ov adjust resistor) is application specific. (see ov adjust and rege n description for details) 5. all resistors have a tolerance of 10%, unless otherwise specified. 6. the cd4050 converts the +15v logic output of the uc-2625 to +5v logic signals. 7. the cd4049 inverts the +15v logic signal from the uc-2625, and converts it to a +5v logic signal. 8. 1% or better, depending on required accuracy. 9. q1 can be either irml2402 or irmu014 or irld014. 10. these high impedance inputs and summing junctions of the operational amplifiers are highly sensitive to noise. 11. these grounds should be closely tied together to reduce ground noise effect. 12. connect hall sensor inputs to motor shaft position sensors that are 120 electrical degrees apart. motors with 60 electrical d egree position sensor coding can be used if one of the position sensor signals are inverted (see figures 9 and 10). 13. may need to increase resistance to reduce excessive noise. figure 12. pw-8x010p6, pw-8x030p6 and pw-8x075p6 torque hook-up using uc-2625 motor controller
18 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 -vco vel -vsum cos -c +c bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 cb sin -s +s agnd +ref u3 -ref gnd a b bit/ inh/ el/ em/ c26 0.1f c27 22f c28 0.1f c29 22f 15 40 +5v r27 120k c25 560pf r28 2.8 m c24 56pf 9 8 7 6 5 10 11 13 14 12 19 20 4 r24 20k r25 20k r26 20k 1 2 r35 10k r29 0.1k r30 0.1k rs rc r31 10k r32 1k 2n2907 +15v 21 cr7 39 18 3 +5v vpp pgm oe ce a0 26 24 33 31 37 35 25 23 29 27 10 9 6 5 8 7 25 24 4 3 a1 a2 a3 a4 a5 a6 a7 a8 a9 20 22 c30 0.1f +5v 27 1 a10 a11 a12 21 23 2 00 01 02 03 04 05 06 07 26 24 33 31 37 35 27c64 (contact factory for code) 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 3 4 7 8 13 14 17 18 q0 q1 q2 q3 q4 q5 q6 q7 2 5 6 9 12 15 16 19 74hct374 clk d7 +5v 1 11 r33 10k hc hb ha 10 11 c31 0.1f c32 0.1f 7 6 1 2 3 4 5 6 16 17 -5v 22 ddc p/n rdc-19220 hall outputs digital position & velocity information which can be used by the dsp controller to close the position and/or velocity loops resolver inputs ddc p/n osc-15801 (see osc-15801 data sheet for design specifications) pa in 3 c2 c2 gnd c1 ref out r36 13k 13 pa out -15v c34 0.1f +15v 18 16 15 c33 0.1f to -ref input #6 to +ref input #5 gnd +15v -15v figure 13. resolver to hall signal conversion circuit
19 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 dirh2h3h1 69108181716141312 hab hbc hca a b c a b c i comp + cw 0100 l h h l h la-b 1 0111 i b + cw 0110 l h h l l ha-c 1 1011 i c + cw 0010 h l h l l hb-c 1 1011 i c + cw 0011 h l h h l lb-a 0 1101 -i b + cw 0001 h h l h l lc-a 0 1110 -i c + cw 0101 h h l l h lc-b 0 1110 -i c - ccw1101 h l h l l hb-c 0 1110 -i c - ccw1001 l h h l l ha-c 0 1110 -i c - ccw1011 l h h l h la-b 0 1101 -i b - ccw1010 h h l l h lc-b 1 1011 i c - ccw1110 h h l h l lc-a 1 1011 i c - ccw1100 h l h h l lb-a 1 0111 i b command in polarity motor rotation uc2625 inputs motor active phase outputs low side high side sw_ -ic _l sw_ gcomp _l sw_ +ib _l sw_ +ic _l sw_ - ib _l i b_pos zero i_b_bipolar i_c_bipolar v iref v irsense_ b i_comp 0 0 0 0 0 u4b lf 147 5 6 4 11 7 + - v+ v- u3 dg201 1 3 2 16 14 15 9 11 10 8 6 7 12 13 5 4 in1 s1 d1 in2 s2 d2 in3 s3 d3 in4 s4 d4 vl vdd gnd vss u4a lf 147 3 2 4 11 1 + - v+ v- r6 4k rn dg r8 4k r9 4k u4c lf147 10 9 4 11 8 + - v+ v- out 2k r10 4k r11 4k rf r12 4k r7 4k c5 1000p rn rf c4 1000p 3k +15v +15v +15v +5v -15v -15v -15v -15v +15v hca hab hbc sw_gcomp_l sw_ - ib_l sw_+ib_l sw_+ic_l sw_ - ic_l +5v (common to all) gnd (common to all) 2k 8k 2k 8k r vri r vr2 note: 0 = on 1 = off c2 100 pf c3 100 pf c1 1000 pf i c_pos (+/- 10v) 0 0 0 u6 201 1 3 2 16 14 15 9 11 10 8 6 7 12 13 5 4 in1 s1 d1 in2 s2 d2 in3 s3 d3 in4 s4 d4 vl vdd gnd vss +15v +5v -15v i b_neg i c _neg v irsense_ c figure 14. current scaling and decommuntation circuit v ref
20 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 1 3 5 7 2 4 6 8 17 19 21 18 20 22 0.69 max (17.526) 2.89 max (73.40) 1.48 max (37.59) pw-8x0xxp6-xxxx m agnum m otor d rive 29 28 27 26 25 0.125 ( 3.17) 0.200 (5.08) side view top view 23 24 16 eq. pin 0.100 centers (2.54 centers) 0.025 sq. (16 places) (0.635) molded in metal insert (2 places) 0.250 x 0.03(thk) (5 places) (6.35 x 0.76) 0.220 (5.58) 0.115 dia (2 places) (2.92 dia) 2.52 (64.00) 2.36 (59.94) 0.100 (2.54) s/n xxxx d/c xxxx tm 0.940 (23.87) 0.738 (18.74) 0.250 (6.35) 0.100 (typ) (2.54) 0.35 (8.89) 0.120 (3.04) .006 1.100 (27.94) 1.000 (25.40) 0.900 (22.86) 0.800 (20.32) 0.200 (5.08) 0.300 ( 7.61) 0.100 (2.54) 0.250 (6.35) 1.140 (28.95) 0.570 (14.48) 2.645 (67.183) 0.250 (6.35) 0.230 (5.84) 0.020 (0.508) (typ) center line center line 0.120 (3.04) 0.550 (13.97) 0.031 (0.79) 0.031 4 places (0.79) figure 15. pw-8x010p6, pw-8x030p6, and pw-8x075p6 outline notes: 1. dimensions are in inches (mm). mounting considerations: for 2 or more modules, minimum spacing center line to center line - 1.5 inches (38.1 mm)
21 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 table 7: pin assignments 2 v cc v cc v cc pin # functions description 1 disable / reset disable / reset disable / reset 3 upper upper upper 4 v cc-rtn v cc-rtn v cc-rtn 5 lower lower lower 6 sleep_mode sleep_mode sleep_mode 7 sc f a ul t sc f a ul t sc f a ul t 8 a ut o reset a ut o reset a ut o reset 17 n/c v ref ov_adj_high (1) (2) 18 n/c v irsense regen_status 19 n/c v irsense_abs n/c 20 n/c v dd ov_adj 21 n/c v dd-rtn n/c 22 n/c oc f a ul t ov_adj_low (1) (3) pw-83010p6 pw-83030p6 pw-83075p6 pw-84010p6 pw-84030p6 pw-84075p6 pw-85010p6 pw-85030p6 pw-85075p6 25 n/c r sense - regen_clamp+ 26 n/c r sense + regen_clamp- 27 v bus + v bus + v bus + 28 output output output 29 v bus - v bus - v bus - 23 n/c n/c n/c 24 n/c n/c n/c power pins control pins notes: (1) connection for external ov adjust resistor only. (2) caution: v bus - voltage present on this pin. (3) caution: v bus + voltage present on this pin.
22 data device corporation www.ddc-web.com pw-8x010p6/8x030p6/8x075p6 j-11/06-0 ordering information pw-8x 0xx p6- x x 0 process requirements: see table 8 temperature grade/data requirements: c = -55c to +100c 2 = -40c to +85c 3 = 0c to +70c g = -55c to +100c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data voltage rating 6 = 600v current rating 010 = 10a 030 = 30a 075 = 75a features 3 = standard ? bridge 4 = standard ? bridge w/ current sense 5 = standard ? bridge w/ regenerative voltage clamp these products contain tin-lead solder finish as applicable to solder dip requirements. table 8. ddc processing - ipc-a-610 process requirement option process 1 3 5 7 burn-in ? ? temperature cycle ? ?
data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 23 j-11/06-0 printed in the u.s.a. 105 wilbur place, bohemia, new york, u.s.a. 11716-2426 for technical support - 1-800-ddc-5757 ext. 7771 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)89-15 00 12-11, fax: +49-(0)89-15 00 12-22 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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